1. Field of the Invention
The present invention generally relates to the formation of integrated circuits having air dielectrics and, more particularly, to the formation of air dielectric structures having reduced capacitance and of improved structural stability or ease and economy of manufacture.
2. Description of the Prior Art
The manufacture of integrated circuits in recent years has exhibited a trend toward larger scales of integration, that is, the placing of larger numbers of electronic devices on a single chip, and reduction of feature size in design rules for the formation of structures therein. The reduction in feature size basically has reduced the spacing between conductive structures within the integrated circuit device. Increases in scale of integration have resulted in not only more devices on a single chip but increases in length of conductors between functional blocks of the integrated circuit device such as a microprocessor.
It has long been recognized that parasitic capacitances impose a limitation on response speed of any electronic device. Further, capacitive coupling between conductive structures is a substantial and significant source of noise and signal distortion. As is well understood in the art, the capacitance developed between any two conductors is a function of the proximity of the conductors, the areas of the conductors and the dielectric constant of the material between the conductors. Therefore, in large scale integrated circuits, the connections between functional blocks of the integrated circuit can present very substantial capacitances due to the length of conductors involved. Increases in the scale of integration and reduction of design rule feature sizes in the integrated circuits also increases the proximity of conductors and increases capacitive coupling. Further, the number of devices and conductors formed on a single chip increases the number of potential sources of noise in the large scale integrated circuit device. Therefore, in critical locations in an integrated circuit device capacitive coupling is commonly reduced by increasing the spacing between conductors and minimizing the length of the portions of conductors which are run in parallel.
These effects of capacitive coupling have become significant even for relatively short conductors (e.g. under 30 microns) under currently feasible design rules. In such a case, where the conductor spacing cannot be increased, the only viable alternative for reduction of capacitance is by reduction of the dielectric constant of the insulating material between the conductors. The dielectric constant of silicon dioxide, the commonly provided insulating material in silicon-based semiconductor devices, is approximately 3.9. Polyimide materials, having a dielectric constant of about 3.1 to 3.5, can thus reduce the capacitive coupling by 10% to 20%. Also, other polymeric compounds are known which have dielectric constants in the ranges of 2.0-2.2 but which exhibit insufficient thermal stability for integrated circuit applications. Therefore, to reduce the dielectric constant below 3.0, it is necessary to provide a So-called air dielectric structure. Since the dielectric constant of air is, by definition, 1.0, the replacement of high dielectric constant material with air can reduce the average dielectric constant of the volume, consisting partially of dielectric material and partially of air, within the electric field between the conductors.
Air dielectric structures are basically formed by the deposition of a removable material as a temporary support for the formation of a conductor. After the conductor is formed, the removable material is etched away or dissolved leaving the conductor suspended above other structures or conductors. Examples of such structures are disclosed in U.S. Pat. Nos. 3,890,636 to Harada et al., 5,034,799 to Tomita et al., 3,925,880 to Rosvold, and 4,933,743 to Thomas et al. However, as can be readily understood, such suspended conductors are not structurally robust and may sag into contact with other conductive areas or be damaged by shock or vibration if not limited in length. Therefore, known air dielectric structures have been limited to very short lengths and have not been applied to reduction of capacitive coupling between longer conductors used to connect functional blocks in large scale integrated circuits.
Air dielectric structures can also be easily damaged during further processing steps such as in the production of additional circuit layers, often encountered in large scale integrated circuits. Since air dielectric structures are essentially voids in the device structure, a degree of structural weakness is unavoidable. Production of multiple layers of conductive patterns in combination with air dielectric structures is particularly difficult since conductors must be formed on highly planar surfaces in order to achieve conductor lines of consistently regular cross-sectional area. Planarization of surfaces for conductor formation requires some degree of mechanical polishing with unavoidable application of shear and compressional forces to the structure. Underlying air dielectric structures are inherently weak in compression perpendicular to the substrate. More importantly, however, air dielectric structures necessarily involve conductors extending in a direction generally perpendicular to the substrate, referred to as studs which define the spacing of the conductors of the air dielectric structures in that direction. For structures involving only short conductors, as in the above-cited Patents, the height of these studs need not be large for reduction of capacitance and the height to transverse dimension aspect ratio is low. Such a low aspect ratio results in generally adequate strength in shear to avoid damage during planarization. However, for longer conductor runs encountered in large scale integrated circuits, it is desirable to increase the spacing between conductive layers to a point where it is not practical to maintain a low aspect ratio of the conductive studs. This limitation derives from the fact that for a given degree of integration density in a layer, increase in size of a feature will reduce the separation between features. Therefore, in large scale integrated circuits, studs are inherently weak in shear. This weakness, when multiple layers containing extended conductor runs must be formed, has limited the incorporation of air dielectric structures and exploitation of the reduction of capacitive coupling potentially available.